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Section11.1Addressing Modes

The ARM instruction set architecture is a Load/Store architecture, which means that data values must be loaded into CPU registers before arithmetic or logic operations can be performed on them. The instructions that load data values from memory, or store data values in memory cannot alter the value.

Instructions that operate on data in registers follow the general pattern:

operation_code    destination_register, source_register(s)

The load instructions follow a similar pattern:

load              destination_register, source_memory_address

But “source” and “destination” are reversed in the pattern of the store instructions:

store             source_register, destination_memory_address

The CPU determines the memory address for a load or store by adding a positive or negative offset to a value in a base register. The way in which the CPU combines these two parts is called the Addressing Mode. The ARM instruction set architecture has three addressing modes:

Immediate

The offset is an unsigned integer that is stored as part of the instruction. It can be added to or subtracted from the value in the base register. If a label is used to specify the address, the assembler uses the pc as the base register and computes the appropriate offset.

Register

The offset is an unsigned integer that is in a register other than the pc. It can be added to or subtracted from the value in the base register.

Scaled Register

The offset is an unsigned integer that is in a register other than the pc. It is shifted by an immediate amount before it is added to or subtracted from the value in the base register.

These addressing modes can affect the value in the base register in three different ways:

Offset

The value in the base register is unchanged.

Pre-indexed

The offset is combined with the value in the base register, and the base register is updated with this new address before being used to access memory.

Post-indexed

The value in the base register alone is used to access memory. Then the the offset is combined with the value in the base register, and the base register is updated with this new address after accessing memory.

The variants of these addressing schemes, and the allowable immediate values, differ between instructions. You need to read the description of each instruction to know what it supports.