Skip to main content
\(\newcommand{\doubler}[1]{2#1} \newcommand{\binary}{\texttt} \newcommand{\hex}{\texttt} \newcommand{\octal}{\texttt} \newcommand{\prog}{\texttt} \newcommand{\lt}{ < } \newcommand{\gt}{ > } \newcommand{\amp}{ & } \)


Keyboard input is a good place to start the discussion of hardware interrupts. It is impossible to know exactly when someone will strike a key on the keyboard, nor how soon the next key will be struck. For example, if a key is struck in the middle of executing the first of the following two instructions:

cmp     r3, NUL         @ end of string?
beq     allDone         @ yes, all done

the keyboard controller will generate an Interrupt Request (IRQ), which will be sent to the CPU. The CPU needs to be used to read the input from the keyboard. Then the CPU needs to return to the instruction sequence it was executing when it was interrupted. Reading from the keyboard will surely affect the Current Program Status Register (cpsr), so the beq instruction would no longer be based on the results of the cmp instruction.

Thus, two essential pieces of information must be saved when an IRQ is received:

  • The Current Program Status Register

  • The return address.

The ARM accommodates these requirements by providing separate spsr, sp, and lr registers for each of the possible exceptions. The CPU responds to the IRQ in the following way:

  1. The CPU switches to the irq mode.

  2. The value in the cpsr is saved in spsr-irq.

  3. The address in the pc is saved in lr-irq.

  4. IRQ interrupts are disabled.

  5. The address corresponding to the IRQ vector, \(\hex{0x00000018}\)e is loaded into the pc.

The CPU will acknowledge an interrupt request only between instruction execution cycles. In our example here, that is just before executing the beq instruction. When the CPU acknowledges the IRQ, the action is similar to that of the bl instruction, except that the return address is stored in the copy of the lr that corresponds to the IRQ, thus preserving the address in the application's lr.

The second part of the branching behavior is carried out by transferring CPU control to the memory address corresponding to the type of exception in the exception vector table. It is the responsibility of the operating system to have placed an appropriate instruction at this memory location.

Returning to our keyboard example, when the user hits the Enter key, the keyboard hardware sends an IRQ to the CPU. The CPU responds as described above, executing the instruction at memory location \(\hex{0x00000018}\text{.}\) It is the responsibility of the operating system to have placed an instruction at that location which will branch to the code that will read the characters from the keyboard.