# Section7.2Programmable Logic Devices¶ permalink

Combinational logic circuits can be constructed from *programmable logic devices* (*PLD*s). The general idea is illustrated in Figure 7.2.1 for two input variables and two output functions of these variables.

Each of the input variables, both in its uncomplemented and complemented form, are inputs to AND gates through fuses. (The S-shaped lines in the circuit diagram represent fuses.) The fuses can be “blown” or left in place in order to program each AND gate to output a product. Since every input, plus its complement, is input to each AND gate, any of the AND gates can be programmed to output a minterm.

The products produced by the array of AND gates are all connected to OR gates, also through fuses. Thus, depending on which OR-gate fuses are left in place, the output of each OR gate is a sum of products. There may be additional logic circuitry to select between the different outputs. We have already seen that any Boolean function can be expressed as a sum of products, so this logic device can be programmed by “blowing” the fuses to implement any Boolean function.

PLDs come in many configurations. Some are pre-programmed at the time of manufacture. Others are programmed by the manufacturer. And there are types that can be programmed by a user. Some can even be erased and reprogrammed. Programming technologies range from specifying the manufacturing mask (for the pre-programmed devices) to inexpensive electronic programming systems. Some devices use “antifuses” instead of fuses. They are normally open. Programming such devices consists of completing the connection instead of removing it.

There are three general categories of PLDs:

- Programmable Logic Array (PLA)
Both the AND gate plane and the OR gate plane are programmable.

- Read Only Memory (ROM)
Only the OR gate plane is programmable.

- Programmable Array Logic (PAL)
Only the AND gate plane is programmable.

# Subsection7.2.1Programmable Logic Array (PLA)¶ permalink

A *programmable logic array* is typically larger than the one shown in Figure 7.2.1, which is already complicated to draw. To simplify the drawing, it is typical to use a diagram as shown in Figure 7.2.2 to specify the design.

This diagram deserves some explanation. Note in Figure 7.2.1 that each input variable and its complement is connected to the inputs of all the AND gates through a fuse. The AND gates have multiple inputs—one for each variable and its complement. In Figure 7.2.2 we use one horizontal line leading to the input of each AND gate to represent multiple wires, one for each variable and its complement. So each AND gate in Figure 7.2.2 has eight inputs even though we draw only one line.

The dots at the intersections of the vertical and horizontal line represent places where the fuses have been left intact. For example, the three dots on the topmost horizontal line indicate that there are three inputs left connected to that AND gate. The output of the topmost AND gate is: \begin{equation*} w' \cdot y \cdot z \end{equation*}

Referring again to Figure 7.2.1, we see that the output from each AND gate is connected to each of the OR gates. Therefore, the OR gates also have multiple inputs—one for each AND gate—and the vertical lines leading to the OR gate inputs represent multiple wires. The PLA in Figure 7.2.2 has been programmed to provide the three functions: \begin{gather} F_1(w,x,y,z) = w' \cdot y \cdot z + w \cdot x \cdot z'\label{mrow-152}\tag{7.2.1}\\ F_2(w,x,y,z) = w' \cdot x' \cdot y' \cdot z'\label{mrow-153}\tag{7.2.2}\\ F_3(w,x,y,z) = w' \cdot y \cdot z + w \cdot x \cdot z'\label{mrow-154}\tag{7.2.3} \end{gather}

# Subsection7.2.2Read Only Memory (ROM)¶ permalink

*Read only memory* can be implemented as a programmable logic device where only the OR plane can be programmed. The AND gate plane is wired to provide all the minterms. Thus, the inputs to the ROM can be thought of as addresses. Then the OR gate plane is programmed to provide the bit pattern at each address.

For example, the ROM diagrammed in Figure 7.2.3 has two inputs, $a_1$ and $a_0$.

The AND gates are wired to give the minterms:

minterm | address |

\(a_1'a_0'\) | \(\binary{00}\) |

\(a_1'a_0\) | \(\binary{01}\) |

\(a_1a_0'\) | \(\binary{10}\) |

\(a_1a_0\) | \(\binary{11}\) |

And the OR gate plane has been programmed to store the four characters (in ASCII code):

minterm | address | contents |

\(a_1'a_0'\) | \(\binary{00}\) | ‘\(0\)’ |

\(a_1'a_0\) | \(\binary{01}\) | ‘\(1\)’ |

\(a_1a_0'\) | \(\binary{10}\) | ‘\(2\)’ |

\(a_1a_0\) | \(\binary{11}\) | ‘\(3\)’ |

You can see from this that the terminology “Read Only *Memory*” is perhaps a bit misleading. It is actually a *combinational logic circuit* that has been *hard wired*. Strictly speaking, memory has a state that can be changed by inputs. (See Section 7.3.)

# Subsection7.2.3Programmable Array Logic (PAL)¶ permalink

In a *Programmable Array Logic* (*PA*) device, each OR gate is permanently wired to a group of AND gates. Only the AND gate plane is programmable. The PAL diagrammed in Figure 7.2.4 has four inputs. It provides two outputs, each of which can be the sum of up to four products. The “\(\times\)” connections in the OR gate plane show that the top four AND gates are summed to produce \(F_1\) and the lower four to produce \(F_2\text{.}\) The AND gate plane in this figure has been programmed to produce the two functions:
\begin{gather}
F_1(w,x,y,z) = w \cdot x' \cdot z + w' \cdot x + w \cdot x \cdot y' + w' \cdot x' \cdot y' \cdot z'\label{mrow-155}\tag{7.2.4}\\
F_2(w,x,y,z) = w' \cdot y \cdot z + w \cdot x \cdot z' + w \cdot x \cdot y \cdot z + w \cdot x \cdot y' \cdot z'\label{mrow-156}\tag{7.2.5}
\end{gather}