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Section 6.2 CMOS Transistors

The general idea is to use two different voltages to represent \(1\) and \(0\text{.}\) For example, we might use a high voltage, say \(+2.5\) volts, to represent \(1\) and a low voltage, say \(0.0\) volts, to represent \(0\text{.}\) Logic circuits are constructed from components that can switch between these the high and low voltages.

The basic switching device in today's computer logic circuits is the metal-oxide-semiconductor field-effect transistor (MOSFET). Figure 6.2.1 shows a NOT gate implemented with a single MOSFET.

Figure 6.2.1 A single n-type MOSFET transistor switch.

The MOSFET in this circuit is an n-type. You can think of it as a three-terminal device. The input terminal is called the gate. The terminal connected to the output is the drain, and the terminal connected to \(V_{SS}\) is the source. In this circuit the drain is connected to positive (high) voltage of a DC power supply, \(V_{DD}\text{,}\) through a resistor, \(R\text{.}\) The source is connected to the zero voltage, \(V_{SS}\text{.}\)

When the input voltage to the transistor is high, the gate acquires an electrical charge, thus turning the transistor on. The path between the drain and the source of the transistor essentially become a closed switch. This causes the output to be at the low voltage. The transistor acts as a “pull down” device.

The resulting circuit is equivalent to Figure 6.2.2(a).

Figure 6.2.2 Single transistor switch equivalent circuit; (a) switch closed; (b) switch open.

In this circuit current flows from \(V_{DD}\) to \(V_{SS}\) through the resistor \(R\text{.}\) The output is connected to \(V_{SS}\text{,}\) that is, \(0.0\) volts. The current flow through the resistor and transistor is

\begin{equation} i = \frac{V_{DD} - V_{SS}}{R}\label{eq-ohm}\tag{6.2.1} \end{equation}

The problem with this current flow is that it uses power just to keep the output low.

If the input is switched to the low voltage, the transistor turns off, resulting in the equivalent circuit shown in Figure 6.2.2(b). The output is typically connected to another transistor's input (its gate), which draws essentially no current, except during the time it is switching from one state to the other. In the steady state condition the output connection does not draw current. Since no current flows through the resistor, \(R\text{,}\) there is no voltage change across it. So the output connection will be at \(V_{DD}\) volts, the high voltage. The resistor is acting as the “pull up” device.

These two voltage states can be expressed in the truth table

input output
low high
high low

which is the logic required of a NOT gate.

There is another problem with this hardware design. Although the gate of a MOSFET transistor draws essentially no current in order to remain in either an on or off state, current is required to cause it to change state. The gate of the transistor that is connected to the output must be charged. The gate behaves like a capacitor during the switching time. This charging requires a flow of current over a period of time. The problem here is that the resistor, \(R\text{,}\) reduces the amount of current that can flow, thus taking longer to charge the transistor gate. (See Section 6.1.2.)

From Equation (6.2.1), the larger the resistor, the lower the current flow. So we have a dilemma—the resistor should be large to reduce power consumption, but it should be small to increase switching speed.

This problem is solved with Complementary Metal Oxide Semiconductor (CMOS) technology. This technology packages a p-type MOSFET together with each n-type. The p-type works in the opposite way—a high value on the gate turns it off, and a low value turns it on. The circuit in Figure 6.2.3 shows a NOT gate using a p-type MOSFET as the pull up device.

\(input\) \(output\)
\(\binary{0}\) \(\binary{1}\)
\(\binary{1}\) \(\binary{0}\)
Figure 6.2.3 CMOS inverter (NOT) circuit.

Figure 6.2.4(a) shows the equivalent circuit with a high voltage input. The pull up transistor (a p-type) is off, and the pull down transistor (an n-type) is on. This results in the output being pulled down to the low voltage.

Figure 6.2.4 CMOS inverter equivalent circuit; (a) pull up open and pull down closed; (b) pull up closed and pull down open.

In Figure 6.2.4(b) a low voltage input turns the pull up transistor on and the pull down transistor off. The result is the output is pulled up to the high voltage.

Figure 6.2.5 shows an AND gate implemented with CMOS transistors.

\(x\) \(y\) \(A\) \(output\)
\(\binary{0}\) \(\binary{0}\) \(\binary{1}\) \(\binary{0}\)
\(\binary{0}\) \(\binary{1}\) \(\binary{1}\) \(\binary{0}\)
\(\binary{1}\) \(\binary{0}\) \(\binary{1}\) \(\binary{0}\)
\(\binary{1}\) \(\binary{1}\) \(\binary{0}\) \(\binary{1}\)
Figure 6.2.5 CMOS AND circuit.

Notice that the signal at point \(A\) is NOT(\(x\) AND \(y\)). The circuit from point \(A\) to the output is a NOT gate. It requires two fewer transistors than the AND operation. We will examine the implications of this result in Section 6.3.