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Section7.3Sequential Logic Circuits

Combinational circuits (Section 7.1) are instantaneous (except for the time required for the electronics to settle). Their output depends only on the input at the time the output is observed. Sequential logic circuits, on the other hand, have a time history. That history is summarized by the current state of the circuit.

System State

A description of the system such that knowing

  • the state at time \(t_0\text{,}\) and

  • the input(s) from time \(t_0\) through time \(t_1\text{,}\)

uniquely determines

  • the state at time \(t_1\text{,}\) and

  • the output(s) from time \(t_0\) through time \(t_1\text{.}\)

This definition means that knowing the state of a system at a given time tells you everything you need to know in order to specify its behavior from that time on. How it got into this state is irrelevant.

This definition implies that the system has memory in which the state is stored. Since there are a finite number of states, the term finite state machine (FSM) is commonly used. Inputs to the system can cause the state to change.

If the output(s) depend only on the state of the FSM, it is called a Moore machine. And if the output(s) depend on both the state and the current input(s), it is called a Mealy machine.

The most commonly used sequential circuits are synchronous—their action is controlled by a sequence of clock pulses. The clock pulses are created by a clock generator circuit. The clock pulses are applied to all the sequential elements, thus causing them to operate in synchrony.

Asynchronous sequential circuits are not based on a clock. They depend upon a timing delay built into the individual elements. Their behavior depends upon the order in which inputs are applied. Hence, they are difficult to analyze and will not be discussed in this book.

Subsection7.3.1Clock Pulses

A clock signal is typically a square wave that alternates between the \(\binary{0}\) and \(\binary{1}\) levels as shown in Figure 7.3.1. The amount of time spent at each level may be unequal. Although not a requirement, the timing pattern is usually uniform.

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Figure7.3.1Clock signals. (a) For level-triggered circuits. (b) For positive-edge triggering. (c) For negative-edge triggering.

In Figure 7.3.1(a), the circuit operations take place during the entire time the clock is at the \(\binary{1}\) level. As will be explained below, this can lead to unreliable circuit behavior. In order to achieve more reliable behavior, most circuits are designed such that a transition of the clock signal triggers the circuit elements to start their respective operations. Either a positive-going (Figure 7.3.1(b)) or negative-going (Figure 7.3.1(c)) transition may be used. The clock frequency must be slow enough such that all the circuit elements have time to complete their operations before the next clock transition (in the same direction) occurs.

Subsection7.3.2Latches

A latch is a storage device that can be in one of two states. That is, it stores one bit. It can be constructed from two or more gates connected such that feedback maintains the state as long as power is applied. The most fundamental latch is the SR (Set-Reset). A simple implementation using NOR gates is shown in Figure 7.3.2.

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Figure7.3.2NOR gate implementation of an SR latch.

When \(Q = 1\) (\(\Leftrightarrow Q' = 0\)) it is in the Set state. When \(Q = 0\) (\(\Leftrightarrow Q' = 1\)) it is in the Reset state. There are four possible input combinations

  • \(S = \binary{0}\text{,}\) \(R = \binary{0}\text{:}\) Keep current state.

    • If \(Q = \binary{1}\) and \(Q' = \binary{0}\text{,}\) the output of the upper NOR gate is \((\binary{0} + \binary{1})' = \binary{0}\text{,}\) and the output of the lower NOR gate is \((\binary{0} + \binary{0})' = \binary{1}\text{.}\)

    • If \(Q = \binary{0}\) and \(Q' = \binary{1}\text{,}\) the output of the upper NOR gate is \((\binary{0} + \binary{0})' = \binary{1}\text{,}\) and the output of the lower NOR gate is \((\binary{1} + \binary{0})' = \binary{0}\text{.}\)

    • Thus, the cross feedback between the two NOR gates maintains the state—Set or Reset—of the latch.

  • \(S = \binary{1}\text{,}\) \(R = \binary{0}\text{:}\) Set.

    • If \(Q = \binary{0}\) and \(Q' = \binary{1}\text{,}\) the output of the upper NOR gate is \((\binary{1} + \binary{0})' = \binary{0}\text{.}\) This is fed back to the input of the lower NOR gate to give \((\binary{0} + \binary{0})' = \binary{1}\text{.}\) The feedback from the output of the lower NOR gate to the input of the upper keeps the output of the upper NOR gate at \((\binary{1} + \binary{1})' = \binary{0}\text{.}\) The latch has moved into the Set state.

    • If \(Q = \binary{1}\) and \(Q' = \binary{0}\text{,}\) the output of the upper NOR gate is \((\binary{1} + \binary{1})' = \binary{0}\text{,}\) and the output of the lower NOR gate is \((\binary{0} + \binary{0})' = \binary{1}\text{.}\) The latch remains in the Set state.

  • \(S = \binary{0}\text{,}\) \(R = \binary{1}\text{:}\) Reset.

    • If \(Q = \binary{1}\) and \(Q' = \binary{0}\text{,}\) the output of the lower NOR gate is \((\binary{0} + \binary{1})' = \binary{0}\text{.}\) This causes the output of the upper NOR gate to give \((\binary{0} + \binary{0})' = \binary{1}\text{.}\) The feedback from the output of the upper NOR gate to the input of the lower keeps the output of the lower NOR gate at \((\binary{1} + \binary{1})' = \binary{0}\text{.}\) The latch has moved into the Reset state.

    • If \(Q = \binary{0}\) and \(Q' = \binary{1}\text{,}\) the output of the lower NOR gate is \((\binary{1} + \binary{1})' = \binary{0}\text{,}\) and the output of the upper NOR gate is \((\binary{0} + \binary{0})' = \binary{1}\text{.}\) The latch remains in the Reset state.

  • \(S = \binary{1}\text{,}\) \(R = \binary{1}\text{:}\) Not allowed.

    • If \(Q = \binary{0}\) and \(Q' = \binary{1}\text{,}\) the output of the upper NOR gate is \((\binary{1} + \binary{0})' = \binary{0}\text{.}\) This is fed back to the input of the lower NOR gate to give \((\binary{0} + \binary{1})' = \binary{0}\) as its output. The feedback from the output of the lower NOR gate to the input of the upper maintains its output as \((\binary{1} + \binary{0})' = \binary{0}\text{.}\) Thus, \(Q = Q' = \binary{0}\text{,}\) which is not allowed.

    • If \(Q = \binary{1}\) and \(Q' = \binary{0}\text{,}\) the output of the lower NOR gate is \((\binary{0} + \binary{1})' = \binary{0}\text{.}\) This is fed back to the input of the upper NOR gate to give \((\binary{1} + \binary{0})' = \binary{0}\) as its output. The feedback from the output of the upper NOR gate to the input of the lower maintains its output as \((\binary{0} + \binary{1})' = \binary{0}\text{.}\) Thus, \(Q = Q' = \binary{0}\text{,}\) which is not allowed.

The state table in Figure 7.3.3.(a) summarizes the behavior of a NOR-based SR latch.

\(S\) \(R\) \(Q\) \(Q_{next}\)
\(\binary{0}\) \(\binary{0}\) \(\binary{0}\) \(\binary{0}\)
\(\binary{0}\) \(\binary{0}\) \(\binary{1}\) \(\binary{1}\)
\(\binary{0}\) \(\binary{1}\) \(\binary{0}\) \(\binary{0}\)
\(\binary{0}\) \(\binary{1}\) \(\binary{1}\) \(\binary{0}\)
\(\binary{1}\) \(\binary{0}\) \(\binary{0}\) \(\binary{1}\)
\(\binary{1}\) \(\binary{0}\) \(\binary{1}\) \(\binary{1}\)
\(\binary{1}\) \(\binary{1}\) \(\binary{0}\) X
\(\binary{1}\) \(\binary{1}\) \(\binary{1}\) X

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(a)SR latch state table.
(b)SR latch state diagram.
Figure7.3.3SR latch. There are two possible inputs, \(\binary{00}\) or \(\binary{01}\text{,}\) that cause the latch to go to state \(\binary{0}\text{.}\) Similarly, \(\binary{00}\) or \(\binary{10}\) cause it to go to state \(\binary{1}\text{.}\) Since the output is simply the state, it is not shown in the state diagram. The input \(\binary{11}\) is not allowed, so it is not shown in the diagram. “X” in the table indicates an indeterminate state. A circuit using this latch must be designed to prevent this input combination.

The inputs to a NOR-based SR latches are normally held at \(\binary{0}\text{,}\) which maintains the current state, \(Q\text{.}\) Its current state is available at the output. Momentarily changing \(S\) or \(R\) to \(\binary{1}\) causes the state to change to \(Set\) or \(Reset\text{,}\) respectively, as shown in the \(Q_{next}\) column.

Notice that placing \(\binary{1}\) on both the \(Set\) and \(Reset\) inputs at the same time causes a problem. Then the outputs of both NOR gates would become \(\binary{0}\text{.}\) In other words, \(Q = Q' = 0\text{,}\) which is logically impossible. The circuit design must be such to prevent this input combination.

The behavior of an SR latch can also be shown by the state diagram in Figure 7.3.3.(b).

A state diagram is a directed graph. The circles show the possible states. Lines with arrows show the possible transitions between the states and are labeled with the input that causes the transition.

The two circles in Figure 7.3.3.(b) show the two possible states of the SR latch—\(\binary{0}\) or \(\binary{1}\text{.}\) The labels on the lines show the two-bit inputs, \(SR\text{,}\) that cause each state transition. Notice that when the latch is in state \(\binary{0}\) there are two possible inputs, \(SR = \binary{00}\) and \(SR = \binary{01}\text{,}\) that cause it to remain in that state. Similarly, when it is in state \(\binary{1}\) either of the two inputs, \(SR = \binary{00}\) or \(SR = \binary{10}\text{,}\) cause it to remain in that state.

The output of the SR latch is simply the state so is not shown separately on this state diagram. In general, if the output of a circuit is dependent on the input, it is often shown on the directed lines of the state diagram in the format “input/output” If the output is dependent on the state, it is more common to show it in the corresponding state circle in “state/output” format.

NAND gates are more commonly used than NOR gates, and it is possible to build an SR latch from NAND gates. Recalling that NAND and NOR have complementary properties, we will think ahead and use \(S'\) and \(R'\) as the inputs, as shown in Figure 7.3.4.

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Figure7.3.4NAND gate implementation of an S'R' latch.

Consider the four possible input combinations.

  • \(S' = \binary{0}\text{,}\) \(R' = \binary{0}\text{:}\) Keep current state.

    • If \(Q = \binary{0}\) and \(Q' = \binary{1}\text{,}\) the output of the upper NAND gate is \((\binary{1} \cdot \binary{1})' = \binary{0}\text{,}\) and the output of the lower NAND gate is \((\binary{0} \cdot \binary{1})' = \binary{1}\text{.}\)

    • If \(Q = \binary{1}\) and \(Q' = \binary{0}\text{,}\) the output of the upper NAND gate is \((\binary{1} \cdot \binary{0})' = \binary{1}\text{,}\) and the output of the lower NAND gate is \((\binary{1} \cdot \binary{1})' = \binary{0}\text{.}\)

    • Thus, the cross feedback between the two NAND gates maintains the state—Set or Reset—of the latch.

  • \(S' = \binary{0}\text{,}\) \(R' = \binary{1}\text{:}\) Set.

    • If \(Q = \binary{1}\) and \(Q' = \binary{0}\text{,}\) the output of the upper NAND gate is \((\binary{0} \cdot \binary{0})' = \binary{1}\text{,}\) and the output of the lower NAND gate is \((\binary{1} \cdot \binary{1})' = \binary{0}\text{.}\) The latch remains in the Set state.

    • If \(Q = \binary{0}\) and \(Q' = \binary{1}\text{,}\) the output of the upper NAND gate is \((\binary{0} \cdot \binary{1})' = \binary{1}\text{.}\) This is fed back to the input of the lower NAND gate to give \((\binary{1} \cdot \binary{1})' = \binary{0}\text{.}\) The feedback from the output of the lower NAND gate to the input of the upper keeps the output of the upper NAND gate at \((\binary{0} \cdot \binary{0})' = \binary{1}\text{.}\) The latch has moved into the Set state.

  • \(S' = \binary{1}\text{,}\) \(R' = \binary{0}\text{:}\) Reset.

    • If \(Q = \binary{0}\) and \(Q' = \binary{1}\text{,}\) the output of the lower NAND gate is \((\binary{0} \cdot \binary{0})' = \binary{1}\text{,}\) and the output of the upper NAND gate is \((\binary{1} \cdot \binary{1})' = \binary{0}\text{.}\) The latch remains in the Reset state.

    • If \(Q = \binary{1}\) and \(Q' = \binary{0}\text{,}\) the output of the lower NAND gate is \((\binary{1} \cdot \binary{0})' = \binary{1}\text{.}\) This causes the output of the upper NAND gate to give \((\binary{1} \cdot \binary{1})' = \binary{0}\text{.}\) The feedback from the output of the upper NAND gate to the input of the lower keeps the output of the lower NAND gate at \((\binary{0} \cdot \binary{0})' = \binary{1}\text{.}\) The latch has moved into the Reset state.

  • \(S' = \binary{0}\text{,}\) \(R' = \binary{0}\text{:}\) Not allowed.

    • If \(Q = \binary{0}\) and \(Q' = \binary{1}\text{,}\) the output of the upper NAND gate is \((\binary{0} \cdot \binary{1})' = \binary{1}\text{.}\) This is fed back to the input of the lower NAND gate to give \((\binary{1} \cdot \binary{0})' = \binary{1}\) as its output. The feedback from the output of the lower NAND gate to the input of the upper maintains its output as \((\binary{0} \cdot \binary{0})' = \binary{1}\text{.}\) Thus, \(Q = Q' = \binary{1}\text{,}\) which is not allowed.

    • If \(Q = \binary{1}\) and \(Q' = \binary{0}\text{,}\) the output of the lower NAND gate is \((\binary{1} \cdot \binary{0})' = \binary{1}\text{.}\) This is fed back to the input of the upper NAND gate to give \((\binary{0} \cdot \binary{1})' = \binary{1}\) as its output. The feedback from the output of the upper NAND gate to the input of the lower maintains its output as \((\binary{1} \cdot \binary{1})' = \binary{0}\text{.}\) Thus, \(Q = Q' = \binary{1}\text{,}\) which is not allowed.

Figure 7.3.5 shows the behavior of a NAND-based \(S'R'\) latch. The inputs to a NAND-based \(S'R'\) latch are normally held at \(\binary{1}\text{,}\) which maintains the current state, \(Q\text{.}\) Its current state is available at the output. Momentarily changing \(S'\) or \(R'\) to \(\binary{0}\) causes the state to change to \(Set\) or \(Reset\text{,}\) respectively, as shown in the “\(Q_{next}\)” column.

\(S'\) \(R'\) \(Q\) \(Q_{next}\)
\(\binary{1}\) \(\binary{1}\) \(\binary{0}\) \(\binary{0}\)
\(\binary{1}\) \(\binary{1}\) \(\binary{1}\) \(\binary{1}\)
\(\binary{1}\) \(\binary{0}\) \(\binary{0}\) \(\binary{0}\)
\(\binary{1}\) \(\binary{0}\) \(\binary{1}\) \(\binary{0}\)
\(\binary{0}\) \(\binary{1}\) \(\binary{0}\) \(\binary{1}\)
\(\binary{0}\) \(\binary{1}\) \(\binary{1}\) \(\binary{1}\)
\(\binary{0}\) \(\binary{0}\) \(\binary{0}\) X
\(\binary{0}\) \(\binary{0}\) \(\binary{1}\) X

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(a)S'R' latch state table.
(b)S'R' latch state diagram.
Figure7.3.5S'R' latch. There are two possible inputs, \(\binary{11}\) or \(\binary{10}\text{,}\) that cause the latch to go to state \(\binary{0}\text{.}\) Similarly, \(\binary{11}\) or \(\binary{10}\) cause it to go to state \(\binary{1}\text{.}\) Since the output is simply the state, it is not shown in the state diagram. The input \(\binary{00}\) is not allowed, so it is not shown in the diagram. “X” in the table indicates an indeterminate state. A circuit using this latch must be designed to prevent this input combination.

Placing \(\binary{0}\) on both the \(Set\) and \(Reset\) inputs at the same time causes a problem, namely that the outputs of both NAND gates would become \(\binary{0}\text{.}\) In other words, \(Q = Q' = \binary{0}\text{,}\) which is logically impossible. The circuit design must be such to prevent this input combination.

So the S'R' latch implemented with two NAND gates can be thought of as the complement of the NOR gate SR latch. The state is maintained by holding both \(S'\) and \(R'\) at \(\binary{1}\text{.}\) \(S' = \binary{0}\) causes the state to be \(\binary{1}\) (Set), and \(R' = \binary{0}\) causes the state to be \(\binary{0}\) (Reset). Using \(S'\) and \(R'\) as the activating signals are usually called active-low signals.

You have already seen that ones and zeros are represented by either a high or low voltage in electronic logic circuits. A given logic device may be activated by combinations of the two voltages. To show which is used to cause activation at any given input, the following definitions are used:

Active-High Signal

The higher voltage represents \(\binary{1}\text{.}\)

Active-Low Signal

The lower voltage represents \(\binary{1}\text{.}\)

The definitions of active-high versus active-low signals vary in the literature. Make sure that you and the people you are working with have a clear agreement on the definitions you are using.

An active-high signal can be connected to an active-low input, but the hardware designer must take the difference into account. For example, say that the required logical input is \(\binary{1}\) to an active-low input. Since it is active-low, that means the required voltage is the lower of the two. If the signal to be connected to this input is active-high, then a logical \(\binary{1}\) is the higher of the two voltages. So this signal must first be complemented in order to be interpreted as a \(\binary{1}\) at the active-low input.

We can get better control over the SR latch by adding two NAND gates to provide a \(Control\) input, as shown in Figure 7.3.6.

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Figure7.3.6SR latch with \(Control\) input.

In this circuit the outputs of both the control NAND gates remain at \(\binary{1}\) as long as \(Control = \binary{0}\text{.}\) Table 7.3.7 shows the state behavior of the SR latch with control.

\(Control\) \(S'\) \(R'\) \(Q\) \(Q_{next}\)
\(\binary{0}\) \(\binary{0}\) \(\binary{0}\)
\(\binary{0}\) \(\binary{1}\) \(\binary{1}\)
\(\binary{1}\) \(\binary{0}\) \(\binary{0}\) \(\binary{0}\) \(\binary{0}\)
\(\binary{1}\) \(\binary{0}\) \(\binary{0}\) \(\binary{1}\) \(\binary{1}\)
\(\binary{1}\) \(\binary{0}\) \(\binary{1}\) \(\binary{0}\) \(\binary{0}\)
\(\binary{1}\) \(\binary{0}\) \(\binary{1}\) \(\binary{1}\) \(\binary{0}\)
\(\binary{1}\) \(\binary{1}\) \(\binary{0}\) \(\binary{0}\) \(\binary{1}\)
\(\binary{1}\) \(\binary{1}\) \(\binary{0}\) \(\binary{1}\) \(\binary{1}\)
\(\binary{1}\) \(\binary{1}\) \(\binary{1}\) \(\binary{0}\) X
\(\binary{1}\) \(\binary{1}\) \(\binary{1}\) \(\binary{1}\) X
Table7.3.7SR latch with Control state table. “–” indicates that the value does not matter. “X” indicates an indeterminate state; a circuit using this latch must be designed to prevent this input combination.

It is clearly better if we could find a design that eliminates the possibility of the “not allowed” inputs. Table 7.3.8 is a state table for a D latch. It has two inputs, one for control, the other for data, \(D\text{.}\) \(D = \binary{1}\) sets the latch to \(\binary{1}\text{,}\) and \(D = \binary{0}\) resets it to \(\binary{0}\text{.}\)

\(Control\) \(D\) \(Q\) \(Q_{next}\)
\(\binary{0}\) \(\binary{0}\) \(\binary{0}\)
\(\binary{0}\) \(\binary{1}\) \(\binary{1}\)
\(\binary{1}\) \(\binary{0}\) \(\binary{0}\) \(\binary{0}\)
\(\binary{1}\) \(\binary{0}\) \(\binary{1}\) \(\binary{0}\)
\(\binary{1}\) \(\binary{1}\) \(\binary{0}\) \(\binary{1}\)
\(\binary{1}\) \(\binary{1}\) \(\binary{1}\) \(\binary{1}\)
Table7.3.8D latch with Control state table. “–” indicates that the value does not matter.

The D latch can be implemented as shown in Figure 7.3.9.

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Figure7.3.9D latch constructed from an SR latch.

The one data input, \(D\text{,}\) is fed to the “\(S\)” side of the SR latch; the complement of the data value is fed to the “\(R\)” side.

Now we have a circuit that can store one bit of data, using the \(D\) input, and can be synchronized with a clock signal, using the \(Control\) input. Although this circuit is reliable by itself, the issue is whether it is reliable when connected with other circuit elements. The \(D\) signal almost certainly comes from an interconnection of combinational and sequential logic circuits. If it changes while the \(Control\) is still \(\binary{1}\text{,}\) the state of the latch will be changed.

Each electronic element in a circuit takes time to activate. It is a very short period of time, but it can vary slightly depending upon precisely how the other logic elements are interconnected and the state of each of them when they are activated. The problem here is that the \(Control\) input is being used to control the circuit based on the clock signal level. The clock level must be maintained for a time long enough to allow all the circuit elements to complete their activity, which can vary depending on what actions are being performed. In essence, the circuit timing is determined by the circuit elements and their actions instead of the clock. This makes it very difficult to achieve a reliable design.

It is much easier to design reliable circuits if the time when an activity can be triggered is made very short. The solution is to use edge-triggered logic elements. The inputs are applied and enough time is allowed for the electronics to settle. Then the next clock transition activates the circuit element. This scheme provides concise timing under control of the clock instead of timing determined more or less by the particular circuit design.

Subsection7.3.3Flip-Flops

Although the terminology varies somewhat in the literature, it is generally agreed that (see Figure 7.3.1.):

Latch

Uses a level based clock signal.

Flip-Flop

Triggered by a clock signal edge.

At each “tick” of the clock, there are four possible actions that might be performed on a single bit—store \(\binary{0}\text{,}\) store \(\binary{1}\text{,}\) complement the bit (also called toggle), or leave it as is.

A D flip-flop is a common device for storing a single bit. We can turn the D latch into a D flip-flop by using two D latches connected in a master/slave configuration as shown in Figure 7.3.10.

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Figure7.3.10D flip-flop, positive-edge triggering.

Let us walk through the operation of this circuit. The bit to be stored, \(\binary{0}\) or \(\binary{1}\text{,}\) is applied to the \(D\) input of the Master D latch. The clock signal is applied to the \(CK\) input. It is normally \(\binary{0}\text{.}\) When the clock signal makes a transition from \(\binary{0}\) to \(\binary{1}\text{,}\) the Master D latch will either Reset or Set, following the \(D\) input of \(\binary{0}\) or \(\binary{1}\text{,}\) respectively.

While the \(CK\) input is at the \(\binary{1}\) level, the control signal to the Slave D latch is \(\binary{1}\text{,}\) which deactivates this latch. Meanwhile, the output of this flip-flop, the output of the Slave D latch, is probably connected to the input of another circuit, which is activated by the same \(CK\text{.}\) Since the state of the Slave does not change during this clock half-cycle, the second circuit has enough time to read the current state of the flip-flop connected to its input. Also during this clock half-cycle, the state of the Master D latch has ample time to settle.

When the \(CK\) input transitions back to the 0 level, the control signal to the Master D latch becomes \(\binary{1}\text{,}\) deactivating it. At the same time, the control input to the Slave D latch goes to \(\binary{0}\text{,}\) thus activating the Slave D latch to store the appropriate value, \(\binary{0}\) or \(\binary{1}\text{.}\) The new input will be applied to the Slave D latch during the second clock half-cycle, after the circuit connected to its output has had sufficient time to read its previous state. Thus, signals travel along a path of logic circuits in lock step with a clock signal.

There are applications where a flip-flop must be set to a known value before the clocking begins. Figure 7.3.11 shows a D flip-flop with an asynchronous preset input added to it.

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Figure7.3.11D flip-flop, positive-edge triggering with asynchronous preset.

When a \(\binary{1}\) is applied to the \(PR\) input, \(Q\) becomes \(\binary{1}\) and \(Q'\) \(\binary{0}\text{,}\) regardless of what the other inputs are, even \(CLK\text{.}\) It is also common to have an asynchronous clear input that sets the state (and output) to \(\binary{0}\text{.}\)

There are more efficient circuits for implementing edge-triggered D flip-flops, but this discussion serves to show that they can be constructed from ordinary logic gates. They are economical and efficient, so are widely used in very large scale integration circuits. Rather than draw the details for each D flip-flop, circuit designers use the symbols shown in Figure 7.3.12.

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Figure7.3.12Symbols for D flip-flops. Includes asynchronous clear (CLR) and preset (PR). (a) Positive-edge triggering; (b) Negative-edge triggering.

The various inputs and outputs are labeled in this figure. Hardware designers typically use \(\overline{Q}\) instead of \(Q'\text{.}\) It is common to label the flip-flop as “\(Qn\)” with \(n = 1, 2,\dots\) for identification. The small circle at the clock input in Figure 7.3.12(b) means that this D flip-flop is triggered by a negative-going clock transition. The D flip-flop circuit in Figure 7.3.10 can be changed to a negative-going trigger by simply removing the first NOT gate at the \(CK\) input.

The flip-flop that simply complements its state, a T flip-flop, is easily constructed from a D flip-flop. The state table and state diagram for a T flip-flop are shown in Figure 7.3.13.

\(T\) \(Q\) \(Q_{next}\)
\(\binary{0}\) \(\binary{0}\) \(\binary{0}\)
\(\binary{0}\) \(\binary{1}\) \(\binary{1}\)
\(\binary{1}\) \(\binary{0}\) \(\binary{1}\)
\(\binary{1}\) \(\binary{1}\) \(\binary{0}\)

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Figure7.3.13T flip-flop state table and state diagram. Each clock tick causes a state transition, with the next state depending on the current state and the value of the input, \(T\text{.}\)

To determine the value that must be presented to the D flip-flop in order to implement a T flip-flop, we refer to Table 7.3.8 for a D flip-flop and add a column for D to the state table as shown in Table 7.3.14.

\(T\) \(Q\) \(Q_{next}\) \(D\)
\(\binary{0}\) \(\binary{0}\) \(\binary{0}\) \(\binary{0}\)
\(\binary{0}\) \(\binary{1}\) \(\binary{1}\) \(\binary{1}\)
\(\binary{1}\) \(\binary{0}\) \(\binary{1}\) \(\binary{1}\)
\(\binary{1}\) \(\binary{1}\) \(\binary{0}\) \(\binary{0}\)
Table7.3.14T flip-flop state table showing the D flip-flop input required to place the T flip-flop in the next state.

By simply looking in the “\(Q_{next}\)” column we can see what the input to the D flip-flop must be in order to obtain the correct state. These values are entered in the \(D\) column. (We will generalize this design procedure in Section 7.4.)

From Table 7.3.14 it is easy to write the equation for D: \begin{align} D &= T' \cdot Q + T \cdot Q'\notag\\ &= T \oplus Q\label{mrow-158}\tag{7.3.1} \end{align} The resulting design for the T flip-flop is shown in Figure 7.3.15.

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Figure7.3.15T flip-flop. (a) Circuit using a D flip-flop. (b) Symbol for a T flip-flop.

Implementing all four possible actions—set, reset, keep, toggle—requires two inputs, \(J\) and \(K\text{,}\) which leads us to the JK flip-flop. The state table and state diagram for a JK flip-flop are shown in Figure 7.3.16.

\(J\) \(K\) \(Q\) \(Q_{next}\)
\(\binary{0}\) \(\binary{0}\) \(\binary{0}\) \(\binary{0}\)
\(\binary{0}\) \(\binary{0}\) \(\binary{1}\) \(\binary{1}\)
\(\binary{0}\) \(\binary{1}\) \(\binary{0}\) \(\binary{0}\)
\(\binary{0}\) \(\binary{1}\) \(\binary{1}\) \(\binary{0}\)
\(\binary{1}\) \(\binary{0}\) \(\binary{0}\) \(\binary{1}\)
\(\binary{1}\) \(\binary{0}\) \(\binary{1}\) \(\binary{1}\)
\(\binary{1}\) \(\binary{1}\) \(\binary{0}\) \(\binary{1}\)
\(\binary{1}\) \(\binary{0}\) \(\binary{1}\) \(\binary{0}\)

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Figure7.3.16JK flip-flop state table and state diagram.

In order to determine the value that must be presented to the D flip-flop we add a column for \(D\) to the state table as shown in Table 7.3.17.

\(J\) \(K\) \(Q\) \(Q_{next}\) \(D\)
\(\binary{0}\) \(\binary{0}\) \(\binary{0}\) \(\binary{0}\) \(\binary{0}\)
\(\binary{0}\) \(\binary{0}\) \(\binary{1}\) \(\binary{1}\) \(\binary{1}\)
\(\binary{0}\) \(\binary{1}\) \(\binary{0}\) \(\binary{0}\) \(\binary{0}\)
\(\binary{0}\) \(\binary{1}\) \(\binary{1}\) \(\binary{0}\) \(\binary{0}\)
\(\binary{1}\) \(\binary{0}\) \(\binary{0}\) \(\binary{1}\) \(\binary{1}\)
\(\binary{1}\) \(\binary{0}\) \(\binary{1}\) \(\binary{1}\) \(\binary{1}\)
\(\binary{1}\) \(\binary{1}\) \(\binary{0}\) \(\binary{1}\) \(\binary{1}\)
\(\binary{1}\) \(\binary{0}\) \(\binary{1}\) \(\binary{0}\) \(\binary{0}\)
Table7.3.17JK flip-flop state table showing the D flip-flop input required to place the JK flip-flop in the next state.

From this it is easy to write the equation for D: \begin{align} D &= J' \cdot K' \cdot Q + J \cdot K' \cdot Q' + J \cdot K' \cdot Q + J \cdot K \cdot Q'\notag\\ &= J \cdot Q' \cdot (K' + K) + K' \cdot Q \cdot (J + J')\notag\\ &= J \cdot Q' + K' \cdot Q\label{mrow-161}\tag{7.3.2} \end{align} Thus, a JK flip-flop can be constructed from a D flip-flop as shown in Figure 7.3.18.

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Figure7.3.18JK flip-flop. (a) Circuit using a D flip-flop. (b) Symbol for a JK flip-flop with asynchronous CLR and PR inputs.