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Section 8.1 Overview

An overall block diagram of a typical CPU is shown in Figure 8.1.1.

Figure 8.1.1. CPU block diagram. The CPU communicates with the Memory and I/O subsystems via the Address, Data, and Control buses. See Figure 1.2.1.

The subsystems are connected together through internal buses. Keep in mind that this is a highly simplified diagram. Actual CPUs are much more complicated. The discussion here is an abstraction that provides a programmer's view of the CPU.

We will now describe briefly each of the subsystems in Figure 8.1.1. The descriptions provided here are generic and apply to most CPUs. Components that are of particular interest to a programmer are described within the context of the ARM ISA later in this chapter.

Program Counter

A special register, typically 32 or 64 bits, that always contains the address of the next instruction to be executed. (Also called an Instruction Pointer.) See Section 8.2 for more details.

L1 Cache Memory

Very fast memory on the CPU chip, although it could be argued that this is not a part of the CPU. As you will see in Section 8.4, each instruction must be fetched from memory. The CPU can execute instructions much faster than they can be fetched. The interface with memory makes it more efficient to fetch several instructions at one time, storing them in L1 cache where the CPU has very fast access to them. Many modern CPUs use two L1 cache memories organized in a Harvard architecture—one for instructions, the other for data. (See Section 1.2.) Its use is generally transparent to an applications programmer.

Instruction Register

Contains the instruction that is currently being executed. Its bit pattern determines what the control unit is causing the CPU to do. Once that action has been completed, the bit pattern in the instruction register can be changed, and the CPU will perform the operation specified by this next bit pattern. Note: ARM manuals use the term “Instruction Register” to mean a special debug register in the CPU, which is beyond the scope of this book.

Control Unit

Controls the activities of all the units in the CPU.


A named group of several bytes of memory within the CPU. Almost all arithmetic and logic operations and data movement operations involve at least one register. See Section 8.2 for more details.

Arithmetic Logic Unit (ALU)

Performs arithmetic and logic operations on groups of bits. The logic circuitry to perform addition is discussed in Section 7.1.1.

Bus Interface

The means for the CPU to communicate with the rest of the computer system—memory and I/O devices. It contains circuitry to place addresses on the address bus, read and write data on the data bus, and read and write signals on the control bus. The Bus Interface on many CPUs interfaces with external bus control units that in turn interface with memory and with different types of I/O buses, e.g., Serial ATA, PCI-E, USB, etc. The external control units are transparent to the applications programmer.

Condition Flags

Bits in a status register that show results of many operations performed by the ALU. For example, addition can set the Carry Flag to show whether or not carry was produced.

We will now look at how the logic circuits discussed in Chapter 6 can be used to implement some of these subsystems.