## Section6.2CMOS Transistors

The general idea is to use two different voltages to represent $$\binary{1}$$ and $$\binary{0}\text{.}$$ For example, we might use a high voltage, say $$+2.5$$ volts, to represent $$\binary{1}$$ and a low voltage, say $$0.0$$ volts, to represent $$\binary{0}\text{.}$$ Logic circuits are constructed from components that can switch between these two voltages.

The basic switching device in today's computer logic circuits is the metal-oxide-semiconductor field-effect transistor (MOSFET). There are several different types of MOSFETs, using different voltage levels and polarities. This is a book about digital computers, so I will only discuss the switching behavior of the MOSFET and will use $$\binary{0}$$ and $$\binary{1}$$ to indicate the state of the switch. I will leave the distinctions between the different types for engineers and physicists to discuss. Figure 6.2.1 shows a NOT gate implemented with a single N-channel MOSFET.

You can think of it as a three-terminal device. The input terminal is called the gate. The terminal connected to the output is the drain, and the terminal connected to the voltage representing logical $$\binary{0}$$ is the source. The drain is connected to the voltage representing logical $$\binary{1}$$ through a resistor, R.

When the input voltage to the MOSFET is at the logical $$\binary{1}$$ level, it is turned on. The path between the drain and the source of the MOSFET essentially becomes a closed switch. This causes the output to be at the voltage of the source, which is logical $$\binary{0}\text{.}$$ The MOSFET acts as a pull-down device. The resulting circuit is equivalent to Figure 6.2.2(a). Figure 6.2.2. Single transistor switch equivalent circuit; (a) switch closed; (b) switch open.

In this circuit current flows from the voltage difference between $$\binary{1}$$ and $$\binary{0}$$ through the resistor R. The problem with this current flow is that it uses power just to keep the output at logical $$\binary{0}\text{.}$$

If the input voltage is switched to the level of logical $$\binary{0}\text{,}$$ the MOSFET turns off, resulting in the equivalent circuit shown in Figure 6.2.2(b). The output is typically connected to another MOSFET’s input (its gate), which draws essentially no current, except during the time it is switching from one state to the other. In the steady-state condition, the output connection does not draw current. Since no current flows through the resistor, $$R\text{,}$$ there is no voltage difference across it. Thus, the output connection will be at the voltage of logical $$\binary{1}\text{.}$$ The resistor is acting as the pull-up device. These two voltage states can be expressed in the truth table:

 $$input$$ $$output$$ $$\binary{0}$$ $$\binary{1}$$ $$\binary{1}$$ $$\binary{0}$$

which is the logic required of a NOT gate.

There is another problem with this hardware design. Although the gate of a MOSFET draws essentially no current to remain in either an on or off state, current is required to cause it to change state. The gate behaves like a capacitor during the switching time. The problem here is that this effective capacitor is being charged through the resistor, $$R\text{,}$$ of the output of the MOSFET that is connected to the input. The equivalent circuit is essentially the same as that in Figure 6.1.4. As you saw in Figure 6.1.5, it takes time to charge the MOSFET gate to switch it.

The engineering dilemma here is that the larger the resistor, the lower the current flow, which reduces power consumption when the MOSFET is in the on state. But the larger resistor also slows the switching speed of the MOSFET connected to the output.

This dilemma is solved with Complementary Metal Oxide Semiconductor (CMOS) technology. This technology packages a P-channel MOSFET together with each N-channel. The P-channel works in the opposite way—a logical $$\binary{1}$$ on the gate turns it off, and a logical $$\binary{0}$$ turns it on. The circuit in Figure 6.2.3 shows a NOT gate using a P-channel MOSFET to replace the resistor as the pull up device.

Figure 6.2.4(a) shows the equivalent circuit with a logical $$\binary{1}$$ input. The pull up MOSFET (a P-channel) is off, and the pull down MOSFET (an N-channel) is on. This results in the output being pulled down to logical $$\binary{0}\text{.}$$ Figure 6.2.4. CMOS inverter equivalent circuit; (a) pull up open and pull down closed; (b) pull up closed and pull down open.

In Figure 6.2.4(b) a logical $$\binary{0}$$ input turns the pull up MOSFET on and the pull down MOSFET off. The result is the output is pulled to $$\binary{1}\text{.}$$

The two main advantages of using CMOS circuits are:

• There is almost no power consumption, except for the very small amount of current that flows during the switching period due to the switching speed difference between N-channel and P-channel MOSFETs. This means there is less heat generated, which is often the limiting factor in chip design.

• The circuit responds much faster because the voltage across MOSFETs changes much more quickly than the voltage across resistors. This allows us to build faster computers, which is the whole point of building them.

Figure 6.2.5 shows an AND gate implemented with CMOS transistors.

Notice that the signal at point $$A$$ is NOT($$x$$ AND $$y$$). The circuit from point $$A$$ to the output is a NOT gate. It requires two fewer transistors than the AND operation. We will examine the implications of this result in Section 6.3.