Section 11.5 Machine Code, Branching
We will now look at the machine code for these two branch instructions. You will see quite a bit of similarity between these instructions and the instructions that implement assignment. For example, the cond bits are in the same location within the instruction. This makes it easier to design the circuitry that decodes the instructions, thus yielding a more efficient design.
Subsection 11.5.1 Conditional Branch
The machine code for the conditional branch instruction is shown in Figure 11.5.1.
The target address is computed by shifting the \(24\) bits in the imm24 field to the left two bit positions and placing zeroes in the two right-most two bit positions. This results in a 26-bit address that is aligned to four-byte address boundaries, which is the alignment of all instructions. This 26-bit value is then sign extended to become a signed 32-bit integer in the range \(-33,554,432\) to \(+33,554,428\text{.}\) This integer is added to the address in the pc, updating the pc to the new address. Thus the b instruction can branch directly \(-33,554,428\) to \(+33,554,432\) bytes from its location—essentially \(\pm 32\)MB. (Recall that the pc has been incremented by four when the b instruction is executed.) The instruction is conditionally executed, depending on the bit pattern in the cond field as given in Table 9.2.1.
Subsection 11.5.2 Branch and Link
The machine code for the branch and link instruction is shown in Figure 11.5.2.
The bl instruction behaves exactly like the instruction, except that it also stores the current value contained in the pc, the address of the instruction immediately following the bl instruction, in the r14.