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Section 11.3 Machine Code, Assignment

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Each assembly language instruction must be translated into its corresponding machine code, including the locations of any data it manipulates. It is the bit pattern of the machine code that directs the activities of the control unit.

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The goal here is to show you that a computer performs its operations based on bit patterns. That is, on-off switches that are connected in ways that were introduced in Chapters 5–8.

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As you read through this material, keep in mind that even though this material is quite tedious, the operations are very simple. Fortunately, instruction execution is very fast, so lots of meaningful work can be done by the computer.

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Subsection 11.3.1 mov instruction, register form

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We start with the register form of the mov instruction. The bit pattern that makes up the machine code is shown in Figure 11.3.1.

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Figure 11.3.1. Register form of mov instruction.

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The four bits in the Rm field specify the number of the source register, and the four bits in the Rd field specify the destination register. The 32 bits in the source register are copied (moved) to the destination register. The instruction is conditionally executed, depending on the bit pattern in the cond field as given in Table 9.2.1. If S = 1 the instruction sets the condition flags according to the value being moved. If S = 0 the condition flags are not affected.

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Subsection 11.3.2 mov instruction, immediate form

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The immediate form of the mov instruction is shown in Figure 11.3.2..

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Figure 11.3.2. Immediate form of mov instruction.

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The four bits in the Rd field speciy the destination register. The 12 bits in the imm12 field are used as explained in Section 11.3.3 to produce a 32-bit value, which is stored in the destination register. The instruction is conditionally executed, depending on the bit pattern in the cond field as given in Table 9.2.1. If S = 1 the instruction sets the condition flags according to the value being moved. If S = 0 the condition flags are not affected.

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Subsection 11.3.3 imm12 field

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Figure 11.3.3. The twelve-bit immediate data field uses eight bits for a data value and four bits to specify the number of two-bit right rotations.

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The eight data bits are zero-extended to 32 bits, and the data is rotated to the right by twice the number of bits specified in the four-bit rot field. Rotation to the right consists of shifting all the bits one position to the right. The lowest-order bit is “rotated” around to the highest-order position.

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For example,

110000000001

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means that

00000000000000000000000000000001

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should be rotated 24 bit positions to the right, giving

00000000000000000000000100000000.
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Subsection 11.3.4 ldr instruction, register form

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Our next example will be the ldr instruction, which will illustrate pc-relative addressing. The bit pattern that makes up the machine code is shown in Figure 11.3.4.

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Figure 11.3.4. Immediate (label) form of ldr instruction.

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A 32-bit value is copied from memory into the register specified by the four bits in the Rt field. The four bits in the Rn specify the base register, which contains the address of a reference memory location. The four bits in the Rm field specify the register that hold an offset value from the base address. This offset value can be shifted by the amount contained in the imm5 field. The type of shift—logical shift left; logical shift right; arithmetic shift right; rotate right— is coded in the two bits in the ty field.

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The instruction is conditionally executed, depending on the bit pattern in the cond field as given in Table 9.2.1. If S = 1 the instruction sets the condition flags according to the value being moved. If S = 0 the condition flags are not affected.

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Common values for Rn are 1011 (r11 or fp) for values in the stack frame, or 1111 (pc) for values in the .text segment. Addressing values in the .text segment is called pc-relative addressing.