Introduction to Computer Organization: ARM Assembly Language Using the Raspberry Pi

Section 17.1 CPU Features

An Exception is an event that causes the CPU to pause the execution of the current code stream and transfer control to a pre-defined location. In general, the following three types of events will cause an exception:

Supervisor Call

An instruction in the program commonly used to request a service from the operating system.

Interrupt

An I/O device notifies the CPU that it is ready to transfer data.

Error Condition

A condition exists within the CPU (typically caused by our programming errors) that cannot be dealt with by the currently running program.

In response to any of these events, the CPU performs an operation that is very similar to the bl instruction. The value in the pc register is copied to an lr register, and another address is placed in the pc register. The net effect is that a function is called, just as in the bl instruction, but the address of the called function is specified by the hardware, and the status of the currently executing program must be saved. Before describing the differences, we discuss what ought to occur in order for the operating system to deal with each of these events

In general, the sequence of responding to an exception is:

1. The currently executing instruction completes execution.

2. The address of the next instruction needs to be saved.

3. The bit settings in the cpsr register need to be saved.

4. The CPU is placed in an appropriate state by modifying bits in the cpsr register.

5. CPU execution is transferred to the code sequence that will handle the cause of the exception.

After the exception has been handled, CPU execution is transferred back to the interrupted code sequence by:

1. Restoring the bit settings in the cpsr register.

2. Loading the address of the next instruction in the interrupted flow into the pc.

The usefulness of the exception handling mechanism for requesting operating system services is not apparent until we discuss privilege levels. As mentioned above, one of the jobs of the operating system is to keep concurrently executing programs from interfering with one another. It uses the Exception Level mechanism in the CPU to ensure it has full control over system hardware resources.

At any given time, the CPU is running in one of four possible exception levels, which are numbered from \(0\) to \(3\text{,}\) with higher numbered levels having more privileges, as shown in Table 17.1.1.

The first instruction of the code that handles an exception is stored in the Exception Vector Table. There is one instruction for each possible type of exception, stored at a hardware-specific location in memory. The structure of the vector table is shown in Table 17.1.2

The ARM architecture includes Banked Registers.

Banked Register

Multiple registers with the same name, with the one in use dependent upon the current processing state.

Each of the modes in Table 17.1.2 has its own sp and lr registers plus a Saved Program Status Register (SPSR). When the CPU takes an exception, it stores the return address in the lr and a copy of the cpsr in the spsr corresponding to the type of exception in the exception vector table. In addition, the Fast Interrupt mode has its own r8–r12 registers. Code running in the fast interrupt mode can use these register to avoid the time involved in saving the general-purpose registers.

Not all exceptions are due to actual program errors. For example, when a program references an address in another part of the program that has not yet been loaded into memory, it causes a page fault exception. The OS must provide a handler that loads the appropriate part of the program from the disk into memory, then continues with normal program execution.