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## Section14.1Logical Instructions

Two numeric operators, addition and subtraction, were introduced in Section 9.2. Many data items are better thought of as bit patterns rather than numerical entities. For example, study Table 2.13.1 and see if you can determine which bit determines the case (upper/lower) of the alphabetic characters.

In order to manipulate individual character codes in a text string, we introduce the bit-wise logical instructions in this section. The bitwise logical operations were shown in the truth tables in Table 4.4.2Table 4.4.4. The instructions available to us to perform the three binary operations are:

AND

Performs a bitwise AND between two integers.

AND{S}{<c>}  {<Rd>,} <Rn>, #<const>           % immediate
AND{S}{<c>}  {<Rd>,} <Rn>, <Rm>{, <shift>}    % register
AND{S}{<c>}  {<Rd>,} <Rn>, <Rm>, <type> <Rs>  % register-shifted register

• If ‘S’ is present the condition flags are updated according to the result. If absent, the condition flags are not changed.

• <c> is the condition code, Table 9.2.1.

• <Rd> specifies the destination register, and <Rm> and <Rn> are the source registers. <Rs> contains the shift amount in the “register-shifted register” form.

• $$-257 \le const \le +256\text{,}$$ or $$const = +256, +260, +264, \ldots, +65280\text{,}$$ or $$const = -261, -265, \ldots, -65281\text{.}$$ This odd sequence of values will be explained in Section 11.3.3

• <shift> and <type> are explained in Section 9.2.3

In the “immediate” form, a bitwise AND is performed between <const> and the value in <Rn>. In the “register” and “register-shifted register” forms, a bitwise AND is performed between the value in <Rm> and the value in <Rn>. If a shift is specified, the value in <Rm> is shifted by the specified amount before the AND is performed. If <Rd> is present the result is stored there and <Rn> is unchanged. If not, the result is stored in <Rn>. The values in <Rm> and <Rs> are unchanged.

ORR

Performs a bitwise inclusive OR between two integers.

ORR{S}{<c>}   {<Rd>,} <Rn>, #<const>           % immediate
ORR{S}{<c>}   {<Rd>,} <Rn>, <Rm>{, <shift>}    % register
ORR{S}{<c>}   {<Rd>,} <Rn, <Rm>, <type> <Rs>   % register-shifted register

• If ‘S’ is present the condition flags are updated according to the result. If absent, the condition flags are not changed.

• <c> is the condition code, Table 9.2.1.

• <Rd> specifies the destination register, and <Rm> and <Rn> are the source registers. <Rs> contains the shift amount in the “register-shifted register” form.

• $$-257 \le const \le +256\text{,}$$ or $$const = +256, +260, +264, \ldots, +65280\text{,}$$ or $$const = -261, -265, \ldots, -65281\text{.}$$ This odd sequence of values will be explained in Section 11.3.3

• <shift> and <type> are explained in Section 9.2.3

In the “immediate” form, a bitwise inclusive OR is performed between <const> and the value in <Rn>. In the “register” and “register-shifted register” forms, a bitwise inclusive OR is performed between the value in <Rm> and the value in <Rn>. If a shift is specified, the value in <Rm> is shifted by the specified amount before the inclusive OR is performed. If <Rd> is present the result is stored there and <Rn> is unchanged. If not, the result is stored in <Rn>. The values in <Rm> and <Rs> are unchanged.

EOR

Performs a bitwise exclusive EOR between two integers.

EOR{S}{<c>}   {<Rd>,} <Rn>, #<const>           % immediate
EOR{S}{<c>}   {<Rd>,} <Rn>, <Rm>{, <shift>}    % register
EOR{S}{<c>}   {<Rd>,} <Rn, <Rm>, <type> <Rs>   % register-shifted register

• If ‘S’ is present the condition flags are updated according to the result. If absent, the condition flags are not changed.

• <c> is the condition code, Table 9.2.1.

• <Rd> specifies the destination register, and <Rm> and <Rn> are the source registers. <Rs> contains the shift amount in the “register-shifted register” form.

• $$-257 \le const \le +256\text{,}$$ or $$const = +256, +260, +264, \ldots, +65280\text{,}$$ or $$const = -261, -265, \ldots, -65281\text{.}$$ This odd sequence of values will be explained in Section 11.3.3

• <shift> and <type> are explained in Section 9.2.3

In the “immediate” form, a bitwise exclusive OR is performed between <const> and the value in <Rn>. In the “register” and “register-shifted register” forms, a bitwise exclusive OR is performed between the value in <Rm> and the value in <Rn>. If a shift is specified, the value in <Rm> is shifted by the specified amount before the exclusive OR is performed. If <Rd> is present the result is stored there and <Rn> is unchanged. If not, the result is stored in <Rn>. The values in <Rm> and <Rs> are unchanged.

The bitwise NOT instruction, mvn, and the bitwise compare instruction, tst, have already been given.

Listings 14.1.1–14.1.2 show how the and instruction can be used to convert lowercase characters to uppercase when some of the characters may already be uppercase. The algorithms of both the main and toUpper functions are very similar to those of main and writeStr in Exercise 13.3.4 and Exercise 13.3.2, respectively, so I go directly to assembly language rather than show the C solution first.