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Section 18.1 Memory Timing

Since the CPU accesses I/O devices via the same buses as memory (see Figure 1.2.1), it might seem that the CPU could access the I/O devices in the same way as memory. That is, I/O could be performed by using the ldr and str instructions to transfer data between the CPU and the specific I/O device. This can be done with many devices, but there are other issues that must be taken into account in order to make it work correctly. One of the main issues lies in the timing differences between memory and I/O. Before tackling the I/O timing issues, let us consider memory timing characteristics.

Two types of RAM are commonly used in PCs.


Holds its values as long as power is on. Access times are very fast. It requires more components to do this, so it is more expensive and larger.


Uses passive components that hold data values for only a few fractions of a second. Thus DRAM includes circuitry that automatically refreshes the data values before the values are completely lost. Less expensive than SRAM, but also much slower.

Most of the memory on the Raspberry Pi is DRAM because it is much less expensive and smaller than SRAM. Of course, each instruction must be fetched from memory, so slow memory access limits program execution speed.

Program execution speed is improved by using cache memory systems made from SRAM.

Cache Memory

A small amount of fast memory placed between the CPU and main memory. When the CPU needs to access a byte, if it is not already in cache memory, that byte, together with several surrounding bytes, are copied from main memory into the cache memory.

There is a high probability that the surrounding bytes will be accessed soon, and the CPU can work with the values in the much faster cache. This is handled by the system hardware.[13][14]

Modern CPUs include cache memory on the same chip, which can be accessed at CPU speeds. Even small cache systems are very effective in speeding up memory access. The CPU in the Raspberry Pi 3 Model B has 16 KB of Level 1 instruction cache, 16 KB of Level 1 data cache, and 512 KB of Level 2 cache (both instructions and data). In contrast, the main memory in the system consists of 1 GB of DRAM.

The important point here is that memory access is matched to the CPU by the hardware. Very seldom is memory access speed a programming issue.