Section 18.3 Bus Timing
Thus far in this book buses have been shown simply as wires connecting the subsystems. Since more than one device is connected to the same wires, the devices must follow a protocol for deciding which two devices can use the bus at any given time. There are many protocols in use, which fall into one of two types:
- Synchronous
Data transfer is controlled by a clock signal. Typically, a centralized bus controller generates the clock signal, which is sent on a separate control line in the bus.
- Asynchronous
Data transfer is controlled by a “handshaking” exchange between the two devices. any asynchronous protocols are handled by the devices themselves over the data and address lines in the bus.
Modern computer systems employ both types of buses. A typical PC arrangement is shown in Figure 18.3.1.
