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List of Figures

1.1 Subsystems of a computer.
2.1 Possible contents of the first sixteen bytes of memory
2.2 Repeat of Figure 2.1 with contents shown in hex.
2.3 A text string stored in memory
3.1 “Decoder Ring” for three-bit signed and unsigned integers.
3.2 Relationship of I/O libraries to application and operating system.
3.3 Truth table for adding two bits with carry from a previous bit addition.
3.4 Truth tables showing bitwise C/C++ operations.
3.5 Truth tables showing C/C++ logical operations.
4.1 The AND gate acting on two variables, x and y.
4.2 The OR gate acting on two variables, x and y.
4.3 The NOT gate acting on one variable, x.
4.4 Hardware implementation of the function in Equation 4.22.
4.5 Hardware implementation of the function in Equation 4.26.
4.6 Mapping of two-variable minterms on a Karnaugh map.
4.7 Karnaugh map for F1(x,y) = x⋅y′+x′⋅y+x⋅y.
4.8 A Karnaugh map grouping showing that F1(x,y) = x⋅y′+x′⋅y+x⋅y = x⋅y′+y.
4.9 Two-variable Karnaugh map showing the groupings x and y.
4.10 Mapping of three-variable minterms on a Karnaugh map.
4.11 Mapping of four-variable minterms on a Karnaugh map.
4.12 Comparison of one minterm (a) versus one maxterm (b) on a Karnaugh map.
4.13 Mapping of three-variable maxterms on a Karnaugh map.
4.14 Mapping of four-variable minterms on a Karnaugh map.
4.15 The XOR gate acting on two variables, x and y.
4.16 A “don’t care” cell on a Karnaugh map.
4.17 Karnaugh map for xor function if we know x = y = 1 cannot occur.
4.18 AC/DC power supply.
4.19 Two resistors in series.
4.20 Two resistors in parallel.
4.21 Capacitor in series with a resistor.
4.22 Capacitor charging over time.
4.23 Inductor in series with a resistor.
4.24 Inductor building a magnetic field over time.
4.25 A single n-type MOSFET transistor switch.
4.26 Single transistor switch equivalent circuit.
4.27 CMOS inverter (NOT) circuit.
4.28 CMOS inverter equivalent circuit.
4.29 CMOS AND circuit.
4.30 The NAND gate acting on two variables, x and y.
4.31 The NOR gate acting on two variables, x and y.
4.32 An alternate way to draw a NAND gate.
4.33 A NOT gate built from a NAND gate.
4.34 An AND gate built from two NAND gates.
4.35 An OR gate built from three NAND gates.
4.36 The function in Equation 4.55 using two AND gates and one OR gate.
4.37 The function in Equation 4.55 using two AND gates, one OR gate and four NOT gates.
4.38 The function in Equation 4.55 using only three NAND gates.
5.1 An adder circuit.
5.2 A half adder circuit.
5.3 Full adder using two half adders.
5.4 Four-bit adder.
5.5 Four-bit adder/subtracter.
5.6 Circuit for a 3×8 decoder with enable.
5.7 Full adder implemented with 3×8 decoder.
5.8 A 2-way multiplexer.
5.9 A 4-way multiplexer.
5.10 Symbol for a 4-way multiplexer.
5.11 Simplified circuit for a programmable logic array.
5.12 Programmable logic array schematic.
5.13 Eight-byte Read Only Memory (ROM).
5.14 Two-function Programmable Array Logic (PAL).
5.15 Clock signals.
5.16 NOR gate implementation of an SR latch.
5.17 State diagram for an SR latch.
5.18 NAND gate implementation of an S’R’ latch.
5.19 State table and state diagram for an S’R’ latch.
5.20 SR latch with Control input.
5.21 D latch constructed from an SR latch.
5.22 D flip-flop, positive-edge triggering.
5.23 D flip-flop, positive-edge triggering with asynchronous preset.
5.24 Symbols for D flip-flops.
5.25 T flip-flop state table and state diagram.
5.26 T flip-flop.
5.27 JK flip-flop state table and state diagram.
5.28 JK flip-flop.
5.29 A 4-bit register.
5.30 A 4-bit register with load.
5.31 8-way mux to select output of register file.
5.32 Four-bit serial-to-parallel shift register.
5.33 Tri-state buffer.
5.34 Four-way multiplexer built from tri-state buffers.
5.35 4-bit memory cell.
5.36 Addressing 1 MB of memory with one 20×220 address decoder.
5.37 Addressing 1 MB of memory with two 10×210 address decoders.
5.38 Bit storage in DRAM.
6.1 CPU block diagram.
6.2 Graphical representation of general purpose registers.
6.3 Condition codes portion of the rflags register.
6.4 Subsystems of a computer.
6.5 The instruction execution cycle.
7.1 Screen shot of the creation of a program in assembly language.
8.1 The stack in Listing 8.3 when it is first initialized.
8.2 The stack with one data item on it.
8.3 The stack with three data items on it.
8.4 The stack after all three data items have been popped off.
8.5 Local variables in the program from Listing 8.5 are allocated on the stack.
8.6 Local variable stack area in the program from Listing 8.5.
9.1 Assembler listing file for the function shown in Listing 9.7.
9.2 General format of instructions.
9.3 REX prefix byte.
9.4 ModRM byte.
9.5 SIB byte.
9.6 Machine code for the mov from a register to a register instruction.
9.7 Machine code for the mov immediate data to a register instruction.
9.8 Machine code for the add immediate data to the A register
9.9 Machine code for the add immediate data to a register
9.10 Machine code for the add immediate data to a register instruction.
9.11 Machine code for the add register to register instruction.
10.1 Flow chart of a while loop.
10.2 Flow chart of if-else construct.
11.1 Arguments and local variables in the stack frame, sumInts function.
11.2 Arguments 7 – 9 are passed on the stack to the sumNine function.
11.3 Arguments and local variables in the stack frame, sumNine function.
11.4 Overall layout of the stack frame.
11.5 Calling function’s stack frame, 32-bit mode.
13.1 Memory allocation for the variables x and y from the C program in Listing 13.6.
14.1 IEEE 754 bit patterns.
14.2 x87 floating point register stack.
16.1 Typical bus controllers in a modern PC.

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